Field of the Invention
Embodiments of the present invention relate generally to static random-access memory (SRAM) and, more specifically, to an SRAM core cell design with write assist.
Description of the Related Art
Typical static random-access memory (SRAM) storage is made up of a collection of SRAM storage cells, where each such cell is configured to store a particular value in a storage node. Each SRAM storage cell is configured to provide the value stored in the storage node in response to a read operation and to modify the value stored in the storage node in response to a write operation.
One aspect of an SRAM cell is the amount of electrical power that the SRAM cell consumes in operation. The amount of electrical power that an SRAM cell consumes is directly proportional to the power supply voltage. Therefore, reducing the power supply voltage typically reduces the amount of power consumed by an SRAM cell, which is advantageous.
However, the power supply voltage that is applied to an SRAM cell typically has to be maintained at or above a minimum value. If the power supply voltage falls below this minimum value, then the SRAM cell does not function predictably, and operations, such as read or write operations, end up producing incorrect results. For example, if the power supply voltage were to fall below the minimum value, then a write operation likely would fail to write a desired value into the SRAM cell.
As the foregoing illustrates, what is needed in the art is an SRAM cell design that allows for a reduced minimum power supply voltage.